(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming high performance self-aligned polysilicon gate field effect transistors with ultra thin gate dielectric.
(2) Background to the Invention and Description of Related Art
The basic MOSFET (metal oxide semiconductor field effect transistor) is typically formed by a self-aligned polysilicon gate process. An region of active silicon region surface for the device is defined on a silicon wafer by an opening surrounded by field oxide isolation(FOX). A gate dielectric, typically silicon oxide, is grown on the exposed silicon regions by thermal oxidation. A polysilicon gate electrode is then patterned over the gate oxide. Source and drain regions are formed in the active silicon region, typically by ion implantation and the device is completed by depositing an insulative layer over the wafer and forming contacts to the source/drain regions and to the gate electrode through openings in the insulative layer.
The performance of the MOSFET is inversely proportional to the gate oxide thickness. Efforts to enhance performance as well as reduce power consumption have driven gate oxide thicknesses to well below 100 Angstroms. It was originally predicted that the physical limit of gate oxide thickness is somewhere around 30xc3x85 because below this thickness carriers are removed by direct tunneling, faster than they can be supplied by thermal generation (Wolf, S., xe2x80x9cSilicon Processing for the VLSI Eraxe2x80x9d, Vol.3, Lattice Press, Sunset Beach, Calif., (1995), p438). However, recent studies by scientists at Bell Laboratories now predict that the physical limit is of the order of 5 atoms which translates to about 14xc3x85 for an SiO2 dielectric.
MOSFET devices are currently being developed which have gate oxide thicknesses as low as 20xc3x85. As one might expect, serious new problems arise when the technology is driven to such levels requiring the design of new methods to deal with them. Although some of these problems may not be totally soluble with today""s technology, it is prudent to selectively exploit situations where the effects of these problems are minimal.
An alternative approach which not only improves device performance by reducing the effective gate oxide thickness but also reduces leakage current is the incorporation of nitrogen in the gate oxide thereby increasing the dielectric constant and increasing hot carrier resistance. Many attempts have been made to improve hot carrier hardness by nitriding relatively thick (500xc3x85) gate oxides in NH3, N2O and NO at high temperatures. In most instances undesirable side effects were encountered (See Wolf, S., loc. cit. pp 648-661).
Hao, et.al., U.S. Pat. No. 5,939,763 shows a method for forming an ultra thin silicon oxynitride layer on a silicon wafer by annealing the wafer first in nitric oxide and then growing the oxynitride in N2O and NO. The resultant oxynitride layer is nitrogen rich at both the Si interface and at it""s upper surface. An obvious drawback of this method is the hazards of using nitric oxide which is applied at atmospheric pressure. Doyle, U.S. Pat. No. 5,891,798 shows a method for depositing a high dielectric constant material, such as a paraelectric or ferroelectric material, onto silicon as a gate dielectric. In order to prevent oxidation of the subjacent silicon by oxygen from the deposited dielectric material, the silicon is first implanted with nitrogen to form a nitrogen enriched surface. In general, forming gate oxides by deposition methods is not desirable because of contamination risks as well as difficulty in achieving stable and reproducible interface characteristics in the channel region.
Soleimani, et. al., U.S. Pat. No. 5,596,218 implants nitrogen into silicon through a sacrificial oxide. After annealing, the nitrogen concentrates in both the oxide and silicon at the SiO2/Si interface. The sacrificial oxide is stripped and a gate oxide is grown. After gate oxide growth, nitrogen in the silicon extends 1000xc3x85 into the silicon and a distance upward into the gate oxide of about 10-20 percent of the oxide thickness. The high concentration of nitrogen in the gate oxide reduces the xe2x80x9chot carrierxe2x80x9d effect by preventing charge build-up in the oxide.
Pan, U.S. Pat. No. 5,750,435 shows a method of implanting nitrogen or fluorine ions at an angle into the gate oxide under the edges of a gate electrode. This hardens the oxide to hot carrier injection which tends to occur in these edge regions. Fulford, et. al., U.S. Pat. No. 5,923,983 cites the introduction of nitrogen into the same critical edge regions during a post-gate-etch oxidation, by adding a nitrogen containing species to the oxidizing gas. Again the object is to harden the oxide edge region near the drain to hot carrier injection.
The efforts of the various references are directed towards achieving hot electron hardness in the regions of the gate oxide wherein this phenomenon occurs. The desirability of increasing the overall dielectric constant of the gate oxide in order to improve device performance has not become an issue until now when gate oxide thicknesses appear to approaching their physical limit. By increasing the dielectric constant of the gate dielectric over conventional silicon oxide, the effective oxide thickness is reduced.
It an object of this invention to provide a method for decreasing the effective gate oxide thickness of gate oxides grown to near their lower physical limit of practical usefulness.
It is yet another object of this invention to provide a method for increasing the dielectric constant of ultra thin gate oxides while concurrently improving their hot carrier hardness and reducing leakage currents.
It is still another object of this invention to provide a method for forming a gate oxide with improved electrical quality, reduced effective oxide thickness while at the same time achieving improved process control.
It is yet another object of this invention to provide a method for increasing the durability of a gate oxide towards attack by halogen based etchants used to pattern polysilicon gate electrodes.
These objects are accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon surface through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, not only decreasing it""s effective thickness with respect to gate capacitance, but also lowers leakage currents by increasing gate oxide resistance to hot carrier injection. In addition, because the initial silicon surface is nitrogen rich, the thermal oxidation rate is reduced. The reduction of oxidation rate improves process control by making the oxidation time and temperature more manageable.
In addition to increasing the dielectric constant of the gate oxide and thereby reducing it""s effective thickness, the incorporation of nitrogen in the oxide also increases the resistance of the oxide to attack by halogen based etchants used to pattern the gate electrode. Patterning the gate electrode comprises anisotropic etching of the polysilicon layer and stopping in the gate oxide. A typical etchant used to etch through the final portion of the polysilicon is HBr. In the patterning process, the gate dielectric must not only halt the HBr etch after the polysilicon has been penetrated in the regions to be cleared, but must also protect the subjacent silicon from etchant penetration during an over-etch period which assures the thorough removal of all vestiges of unwanted polysilicon. Nitrogen enrichment of the gate oxide, according to the method taught by this invention, decisively increases the silicon-to-gate oxide selectivity and thereby provides the added benefit to the gate patterning process.